1. Field of the Invention
The present invention relates to a process for producing a semiconductor substrate, particularly to a process for producing a semiconductor substrate which is applicable to semiconductor devices, integrated circuits, fine mechanical devices, and the like, or which is suitable for dielectric separation, and electronic devices and integrated circuits formed on a monocrystalline semiconductor layer on an insulator.
2. Related Background Art
In recent years, integrated circuits have come to be remarkably more highly integrated. As the results, higher precision is required in of processing of the substrate surface thereof to meet much severer conditions. If the surface becomes rough during the processing, the roughness needs to be eliminated for obtaining a flat smooth surface. Contamination with impurity and particles have also to be avoided.
Polishing is generally employed for flattening the surface of a monocrystal. The polishing is conducted such that the surface to be polished is pressed against polishing cloth made of urethane and is rubbed with it while a polishing liquid composed of a neutral solution or an alkaline solution (e.g., KOH) and a polishing particulate material suspended therein is dropped thereto, to abrade and flatten the surface. For example, a monocrystalline silicon surface is polished and flattened by dropping a suspension, in an alkaline solution (e.g., KOH), of colloidal silica composed of silicon oxide as polishing particulate material.
With the modern technique of polishing of semiconductor substrates, practicably achievable level of surface roughness is several nm in terms of p-v (maximum-minimum difference) and about 0.1 nm in terms of rms (mean square deviation).
Another technique of flattening is heat-treatment.
S. Nakashima and K. Izumi reported that the roughness of the surface having a great number of concavities of several tens of nm was eliminated by heat-treatment at 1260.degree. C. in a nitrogen atmosphere for 2 hours, or at 1300.degree. C. in an argon atmosphere containing 0.5% oxygen for 4 hours, but the roughness did not change by heat-treatment at 1150.degree. C. (J. Mater. Res. (1990) Vol.5, No.9, p.1918).
T. Sakamoto, et al. reported that, in an Si-MBE apparatus, steps on the surface of Si wafer decreased, and the luminance at the mirror reflection point in reflective high-speed electron diffraction increased monotonously with annealing time when the spontaneously formed oxide film was removed, an Si layer was grown, and the layer was annealed in a high vacuum at a high temperature (700.degree. C. to 1000.degree. C.), as a method for flattening a wafer at an atomic level (Denki Tsushin Gakkai Gijutsu Hokoku (Technical Bulletin of Electro-communication Society) SSD86-25, (1986) p.47).
N. Nakamura, et al. found that rectangular projections and concavities having height and width of about 1 .mu.m on a surface of Si were deformed during heat treatment in ultra high vacuum in an MBE apparatus (Journal of Applied Physics, Vol. 68 (1990), p.3038). They reported that it is important, for causing the deformation, to eliminate the spontaneously formed oxide film from the Si surface to provide a surface that is clean in atomic level.
Aoyama, et al. reported that surface roughness of an Si substrate changed on exposure to hydrogen-diluted fluorine having been excited by UV light, and in particular, a (111) Si surface was flattened by 0.1 to 0.2 nm in terms of rms, and they suggested that this change is caused by rate-controlled oxidation of the (111) surface and removal of the resulting oxide by HF (Ohyo Butsuri Gakkai Gakujutsu Koenkai (Meeting for Scientific Lectures of Applied Physical Society (1991), 12a-B-6).
Of the above-described flattening methods, a polishing method is illustrated in FIGS. 13A and 13B, where the numeral 11 indicates a substrate; 12, irregularity of the substrate surface; 13, a surface state before the polishing; and 14, a surface state after the polishing. As shown in FIG. 13A, the rough surface of monocrystal is removed a certain amount of the surface layer by polishing to obtain a smoothened and flattened surface as shown in FIG. 13B. In other words, polishing for elimination of roughness removes inevitably a certain amount of the surface layer, and variation in the polishing procedure causes disadvantageously variation of the thickness of the polished surface layer. Therefore, in the case where the outermost surface or vicinity thereto of a monocrystal is utilized, the removal of the surface layer by polishing is not suitable for smoothening and flattening of the surface insofar as the thickness of the monocrystal is important. Moreover, the surface layer of monocrystal provided by polishing usually has defects such as distortion and dislocation caused by the polishing operation. After the polishing, such defects need to be eliminated by etching of several hundreds of nm to several .mu.m, or at least several tens of nm, of the surface layer.
The processing of semiconductor devices is practiced in a clean room where contaminating particles are removed ultimately. The polishing process, which is a dust-forming process, has to be separated from other processes, and special care has to be taken in delivery of the intermediate products to or from the separated processes. Therefore the polishing is not practical in the device production.
On the other hand, the flattening by heat-treatment in a nitrogen atmosphere involves problems below, because of the treatment in a high temperature exceeding 1260.degree. C. for a long time:
(1) A specially designed treating-furnace is required which employs a high-temperature-resistant construction material such as SiC in the semiconductor process, since the temperature exceeds the maximum resistance temperature of a silica tube (a silica tube may be distorted at a temperature of 1200.degree. C.).
(2) A number of slip lines may be introduced to the monocrystal owing to temperature distribution in the substrate or temperature variation on putting the substrate into or out from the furnace, since the treating temperature is near the melting point of silicon.
(3) Impurity may diffuse and redistribute, in the case where an impurity such as boron and phosphorus is preliminarily introduced locally in monocrystal layer.
To solve the above problems, a method is being sought which is capable of forming a surface having the same level of flatness as or a higher level than that achieved by polishing, at a temperature for a production process of devices, integrated circuits, etc. or a lower temperature without removal of monocrystal surface.
One of the flattening methods, in which the temperature is adaptable to the process and the surface layer of the monocrystal is not removed, is a heat-treatment in the aforementioned MBE (molecular beam epitaxy) apparatus. This technique, however, relates to a flattening of steps at an atomic layer level (less than 1 nm) or deformation of grooves on a surface by migration of surface atomic layer, but does not relates to elimination of roughness of about 1e3 nm to about 1 nm in terms of p-V. Further, in this technique, a high vacuum or ultra-high vacuum (lower than 1.times.10.sup.-11 Torr) is required since the removal of an oxide film on the surface and prevention of re-oxidation are indispensable. However, heating in high vacuum involve problems of nonuniform temperature distribution and long time required for cooling because of lack of heat transfer by convention. If heating is conducted with an exothermic body, a further problem of diffusion of an impurity from the exothermic body arises.
Furthermore, the MBE process is expensive in comparison with the polishing treatment because of the necessity of high performance of a pump for the a large volume of an ultra-high vacuum chamber and the cost of the MBE chamber, and additionally involves the above-mentioned problem of the heat source. Therefore, the MBE is not suitable for industrial mass-production processes where a large area of substrate is treated or a large number of substrates are treated simultaneously. Nakamura, et al. (Ohyo Butsuri Gakkai Gakujutsu Koenkai (Meeting for Scientific Lectures of Applied Physical Society (1990), 27a-T-2) pointed out that, in the MBE process, defects are introduced in a high density into monocrystal with deformation over 800.degree. C., which are caused by oxygen and carbon. Thus, at a high temperature where surface atoms can readily move, defects is disadvantageously introduced.
The flattening by hydrogen-diluted fluorine gas which has been excited by UV light leads to improvement by only from about 0.1 to 0.2 nm in terms of rms, and is limited in capability of flattening the roughness, being not capable of improving roughness at the same level as polishing. Furthermore, this method involves plane orientation dependence, and the (100) plane is roughened adversely.
On the other hand, formation of monocrystalline Si semiconductor layer on an insulator is well known as silicon-on-insulator (SOI) technique. Many investigations have been made thereon since the devices made by the SOI technique have many advantages which are not achievable with a bulk Si substrate for usual Si integrated circuits. The advantages brought about by the SOI technique are as below:
1. Ease of dielectric separation, and practicability of high integration,
2. High resistance against radioactive rays,
3. Low floating capacity, and practicability of high speed operation,
4. Practicability of omission of a welling step,
5. Practicability of prevention of latching-up,
6. Practicability of thin film formation for complete depletion type field effect transistor, and so forth.
In order to realize the aforementioned advantages in device characteristics, investigations have been made on the methods of forming the SOI structure for the last few decades. The results of the investigations are collected in the literature, for example: Special Issue: "Single-crystal silicon on non-single-crystal insulators;" edited by G. W. Cullen, Journal of Crystal Growth, Vol. 63, No. 3, pp. 429-590 (1983).
Formerly, the SOS technique (silicon-on-sapphire) is known which heteroepitaxially forms Si on monocrystalline sapphire substrate by CVD (chemical vapor deposition). This technique, although successful as completed SOI technique, is not widely applied because of many crystal defects caused by insufficient coherency of the lattice at the interface between the Si layer and the underlying sapphire substrate, migration of aluminum from the sapphire substrate to the Si layer, and, above all, the high cost of the substrate and difficulty in enlarging the area thereof.
In recent years, the SOI structure without use of the sapphire substrate is going to be realized. This attempt is made in two methods:
(1) method of oxidizing a surface of an monocrystalline Si substrate, forming an aperture in the oxidized layer to uncover locally the Si substrate, and growing Si epitaxially in a lateral direction using the uncovered Si as the seed to form an monocrystalline Si layer on the SiO.sub.2 (deposition of Si on SiO.sub.2), and
(2) method of forming SiO.sub.2 under the monocrystalline Si substrate by use of the monocrystalline Si substrate itself as the active layer (no deposition of Si layer).
The means for practicing the method (1) above include direct epitaxial growth of monocrystalline Si layer in a lateral direction by CVD; deposition of amorphous Si and subsequent epitaxial growth in solid in a lateral direction by heat treatment; growth of amorphous or polycrystalline Si into monocrystalline layer by melting-recrystallization by focusing thereon an energy beam such as electron beam and laser light; and zone melting recrystallization. These methods have both advantages and disadvantages, still involving problems in controllability, productivity, uniformity, and quality of the products. Therefore, none of the above methods has been practiced industrially.
For example, the CVD process requires sacrificial oxidation. The solid growth results in low crystallinity. The beam annealing process involves problems in treating time, control of superposition of the beam and focus adjustment. Among the above methods, zone melting recrystallization is most highly developed, and has been employed for experimental production of relatively large integrated circuits. This method, however, still causes crystal defects in subgrain boundary, etc., and does not give a minority carrier device.
The method (2) above, which do not use the Si substrate as the seeds for epitaxial growth, are practiced in the three ways below:
1. A surface of a monocrystalline Si substrate is etched anisotropically to form V-shaped grooves on the surface. An oxide film is formed thereon. On the oxide film, a polycrystalline Si layer is deposited in a thickness that is nearly the same as the Si substrate. Then the Si substrate is abraded at the backside to form dielectrically separated monocrystalline Si regions surrounded by the V-shaped grooves on the thick polycrystalline Si layer. Although this technique gives satisfactory crystallinity, it involves problems in control and productivity in the process of depositing polycrystalline Si in a thickness of as much as several hundred .mu.m and in the process of abrading the monocrystalline Si substrate from the backside to leave only the separate active Si layer.
2. An SiO.sub.2 layer is formed on a monocrystalline Si layer by oxygen ion implantation. This method is called SIMOX (separation by ion implanted oxygen). This process exhibits excellent coherency with the Si process, and is the most highly developed technique at the moment. However, the process requires implantation of oxygen ions as much as 10.sup.18 ions/cm.sup.2 to form the SiO.sub.2 layer, and the implantation takes long time, so that the productivity is not high, and the wafer cost is high. Furthermore, the product has many remaining crystal defects, and does not have satisfactory quality for industrial production of minority carrier devices.
3. The SOI structure is formed by dielectric separation by oxidation of porous Si. In this method, on a surface of a P-type monocrystalline Si substrate, an N-type Si layer is formed in an island shape by proton ion implantation (Imai, et al.: J. Crystal Growth, vol. 63, 547, (1983)), or by epitaxial growth and patterning, then the P-type Si substrate only is made porous by anodization in an HF solution so as to surround the island-shaped Si regions, and the N-type Si layers are separated dielectrically by accelerated oxidation. This method has disadvantage that the freedom in device design is frequently restricted since the Si region to be separated has to be decided prior to the device production process.
On the other hand, a light-transmissive substrate typified by glass allows Si to grow only into an amorphous or polycrystalline layer under the influence of the disorderness of the crystal structure of the glass, and is unsuitable for production of devices of high performance. Simple deposition of Si on such a substrate will not give excellent monocrystal layer because of the amorphous structure of the substrate. The light-transmissive substrate is important in constructing a light-receiving element for a contact sensor, a projection type liquid crystal image displaying apparatus, and the like. In order to provide a sensor or an image element (picture element) of a display apparatus in higher density, higher resolution, and higher fineness, extremely high performance of the driving device is required. Therefore, the device on a light-transmissive substrate have to be made from monocrystal layer having excellent crystallinity.
In other words, amorphous Si or polycrystalline Si will not generally give a driving device which exhibits the satisfactory performance required or to be required in the future because of many defects in the crystal structure.
On a light-transmissive substrate, however, none of the above methods for a monocrystalline Si substrate is suitable for forming a monocrystal layer with good quality.